This invention relates to programmable logic devices (PLDs), and, more particularly, to specialized processing blocks which may be included in such devices.
As applications for which PLDs are used increase in complexity, it has become more common to design PLDs to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a PLD that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
One particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, a PLD sold by Altera Corporation, of San Jose, Calif., under the name STRATIX® II includes DSP blocks, each of which includes four 18-by-18 multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed. In order to support four 18-by-18 multiplication operations, the block has 4×(18+18)=144 inputs. Similarly, the output of an 18-by-18 multiplication is 36 bits wide, so to support the output of four such multiplication operations, the block also has 36×4=144 outputs.
However, those inputs and outputs may not be used in every mode in which the DSP block can operate. For example, if the DSP block is configured as a finite impulse response (FIR) filter, with 18-bit data and coefficients, each block may be used to perform the summation of four 18-by-18 multiplications to form a 4-tap sub-block of a longer FIR filter. In this case, the number of inputs is 4×(18+18)=144 lines, but the output is only 38 bits wide even though the DSP block is able to support 144 output lines. Similarly, in a 36-by-36 bit multiplication, all four internal multipliers are used but only (36+36)=72 input lines and 72 output lines are used (even thought there are 144 input lines and 144 output lines). Hence, in that configuration the input lines are not used fully even though the core of the DSP block is fully used.
Input/output (I/O) drivers and lines can consume significant device area. Indeed, in a DSP block of the aforementioned STRATIX® II PLD, I/O resources consume approximately 50% of the DSP block area. And yet, as discussed above, they are not always used. At the same time, they cannot be eliminated because all of the potential configurations of the block have to be supported.
It would be desirable to be able to reduce the area of a PLD consumed by a specialized processing block such as a DSP block without losing functionality of the block.